Intel’s first Xe HPC high-performance independent display kernel map leaked official

The Intel Xe discrete graphics card is steadily advancing, divided into four different architectures. Among them, the core display version, mobile single display version, and desktop single display version based on the Xe LP low-power architecture have all been released and shipped.

There are high-performance versions of Xe HPG, Xe HP, Xe HPC, covering different fields like games, high-performance computing, data centers, artificial intelligence, etc. Xe HPG has been lit, Xe HP is in trial production, and Xe HPC is in development Among.

Raja Koduri, Intel’s senior vice president, chief architect, and general manager of architecture graphics and software revealed the news today.

For the first time, he declared the internal images of the Xe HPC chip and revealed that it is ready to light up (Power On), and As many as 7 different chip technologies are applied in the unified package-it should include multiple manufacturing processes and packaging processes.

Although there is no information, from the image, this Xe HPC chip adopts a 2-Tile dual-core package, each should have 8 computing cores, but it is not clear how many execution units are divided into, and externally it is There is a whole of 8 HBM video memory stacks, and there is a chip of unknown purpose in the corner, suspected to be an independent cache or interconnect module.

Intel announced the first product based on the Xe HPC architecture as early as the end of 2019, code-named ‘Ponte Vecchio’, produced by 7nm process, Foveros 3D, Co-EMIB hybrid packaging, supporting HBM memory, CXL high-speed interconnection, etc., Ramo consistency Cache technology is oriented to HPC high-performance computing, AI artificial intelligence and other fields.

Raja claims that the Xe HPC architecture is highly scalable and can easily achieve 10,000 execution units. Each unit is a new design. The FP64 double-precision floating-point performance is 40 times higher than the current one. It is connected through the XEMF (Xe Memory Fabric) bus. HBM video memory and both CPU and GPU can access the Rambo cache.

According to the latest information released by Intel,  the base module (Base Tile) in the Xe HPC chip uses the Intel 10nm SuperFin process, and the computing module (Compute Tile) uses both Intel’s next-generation process (7nm?) and a third-party process (TSMC 7nm?), Rambo cache module uses Intel 10nm SuperFin enhanced technology, Xe Link I/O interconnect input and output module is a third-party technology.

For comparison, Xe LP is 10nm SuperFin, Xe HP is 10nm SuperFin enhanced version, and Xe HPG is outsourced.