Technology
Logic density of 3nm process is higher than 5nm: TSMC
According to the latest report, China’s IC design Industry 2021 Conference and Wuxi IC Industry Innovation Development Summit Forum will be held on December 22. Luo Zhenqiu, general manager of TSMC (Nanjing) Co., Ltd., gave a keynote speech on “The New Era of Semiconductor Industry”.
Luo Zhenqiu announced that although many people say that Moore’s Law is slowing down or gradually disappearing, in fact, TSMC is using new technology to prove that Moore’s Law is still advancing.
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TSMC’s 7nm process was launched in 2018, 5nm was launched in 2020, and the 3nm process will be launched as scheduled in 2022, and the 2nm process is also being developed smoothly.
Moreover, according to the roadmap displayed by TSMC from 5nm to 3nm, the logic density of the transistor can be increased by 1.7 times, performance can be increased by 11%, and power consumption can be reduced by 25%-30% under the same performance.
1. Change the structure of the transistor: Samsung will adopt a new “Gate Surround Transistor” (GAA) structure in the 3nm process, while TSMC 3nm will still use the FinFET structure. However, TSMC has developed the Nanosheet/Nanowire transistor structure (similar to GAA) for more than 15 years and has achieved very solid performance.
2. Change the material of the transistor: You can use two-dimensional materials to make the transistor. This will make the power consumption control better, and the performance will be stronger.
Furthermore, Luo Zhenqiu also said that in the future, 3D packaging technology will be used to improve chip performance and reduce costs. At present, TSMC has integrated advanced packaging-related technologies into a “3DFabric” platform.
In addition, TSMC will also apply the 5nm process platform “N5A” to automotive chips in ADAS and smart digital cockpits. It is expected to be launched in the third quarter of 2022 and can meet automotive process standards such as AEC-Q100, ISO26262, and IATF16949.