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SK Hynix develops DDR5 DRAM CXL memory, supports PCIe 5.0 x8 lanes
SK Hynix announced the development of the first CXL memory sample based on DDR5 DRAM. The shape and size of the product is EDSFF (Enterprise & Data Center Standard Form Factor) E3.S, supports PCIe 5.0 x8 channels, uses a CXL controller, and uses DDR5 standard DRAM.
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Officially, CXL (Compute Express Link) based on PCIe (Peripheral Component Interconnect Express) is a new standardized interface developed for efficient use of CPU, GPU, accelerator, memory, etc. The first CXL memory developed by SK Hynix is a 96GB product using the latest technology node 1anm DDR5 24Gb.
Moreover, SK Hynix plans to present at the Flash Memory Summit (FMS) at the beginning of August this year, Intel Innovation at the end of September, and the Open Compute Project (OCP) Global Summit in October.