Technology
Apple’s embedded cores are accelerating development of the RISC-V architecture
Apple is moving its embedded chip core instruction set from the ARM architecture to the RISC-V architecture, and Google will also implement the SiFive X280 on the TPU. Main part of the design.
For example, the current Apple A15 Bionic chip has more than a dozen Arm-based CPU cores distributed on the chip for various tasks that are not directly exposed to the user. Semianalysis can confirm that these cores are actively moving towards RISC-V architecture in future generations of hardware.
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Some have also pointed out that RISC-V, as an open source hardware architecture in BSD, will not use RISC-V directly according to Apple’s consistent style of behavior, and that it will be closed source after magical modification (this Apple may name ISA) with its own closed-source system for overall marketing, similar to the instruction set mode in CPUs after the A10.
In Apple silicon design, the core is a very important part. For example, in the M1, there are more than 30 cores responsible for various workloads that are not system related, such as WiFi/Bluetooth, interface retiming, touchpad control, cores for NAND chips, etc., all of which have their own firmware. Is. , And the SOC peripherals provide support for the function circuit.
Currently, most of these cores are based on Arm M-series or low-end A-series IP, and Apple is currently exploring ways to replace these cores with RISC-V.
Given that a great deal of software depends on the main big one. Little to run, other smaller SoC functions are migrated to the odd ISA with only a few firmware tweaks. More importantly, Apple can save a huge amount of license fees from this. In Cook’s view, there’s no reason for Apple not to do so.
According to Apple’s official introduction, the A16 Bionic chip is composed of two high-performance cores and four high-efficiency cores. Graphics processor with 50% more memory bandwidth, ideal for running graphics-intensive games and apps, and a new 16-core neural network engine capable of processing up to 17 trillion operations per second, delivering high performance in low conditions and enabling full-day battery. Life